Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. A typical circuit used to determine sensitivity of the semiconductor circuit to human handling includes a capacitor and resistor that emulate a human body resistor-capacitor (RC) time constant. The capacitor is preferably 100 pF, and the resistor is preferably 1500Ω, thereby providing a 150-nanosecond time constant. A semiconductor device is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, the capacitor is initially charged to a predetermined stress voltage and discharged through the resistor and the semiconductor device. This predetermined stress voltage preferably includes both positive and negative stress voltages with respect to a reference pin or terminal. A post stress current-voltage measurement determines whether the semiconductor device is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge.
A charged-device ESD test is another common test method for testing semiconductor device sensitivity. This method is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply connected in series with a current limiting resistor. The semiconductor device forms a capacitor above a ground plane that is typically 1-2 pF. A low impedance conductor forms a discharge path having an RC time constant typically two orders of magnitude less than a human body model ESD tester. In operation, the semiconductor device is initially charged with respect to the ground plane to a predetermined stress voltage. The semiconductor device is then discharged at a selected terminal through the low impedance conductor. This connection produces a high-voltage, high-current discharge in which a magnitude of the initial voltage across the semiconductor device approaches that of the initial stress voltage.
A particular protection circuit design problem arises when protection circuits are connected to an external terminal that receives both positive and negative voltages with respect to a reference terminal such as VSS during normal circuit operation. Many analog and mixed signal circuits must accommodate such positive and negative signal voltage swings. These signal voltage swings will turn on conventional transistors during normal circuit operation. These positive and negative voltage swings, therefore, preclude a use of many conventional protection circuit devices. Furthermore, the protection circuits of analog and mixed signal circuits must conduct current in a low impedance state in response to an external ESD pulse. They must also remain in a high impedance state during normal circuit operation, and they must protect against positive and negative ESD pulses outside of normal operating parameters as well.
Referring now to FIG. 4, there is a dual silicon-controlled-rectifier (SCR) circuit of the prior art. This dual SCR circuit includes SCR circuits 406 and 408 connected between external terminal or bond pad 400 and reference terminal 410. The SCR circuits are arranged in parallel with opposite polarities. Thus, SCR 406 has an anode connected to external terminal 400 and a cathode connected to reference terminal 410 to conduct in response to positive ESD pulses at external terminal 400. SCR 408 has a cathode connected to external terminal 400 and an anode connected to reference terminal 410 to conduct in response to negative ESD pulses at external terminal 400. These circuits offer limited flexibility in adjustment of trigger voltage thresholds. They are typically activated by a PN junction avalanche threshold voltage in response to a relatively high voltage ESD pulse. This high voltage ESD pulse may damage thin oxide devices in protected circuit 404 prior to activating either SCR. These circuits have a further disadvantage that two of them are required for bi-directional operation in response to both polarities of ESD stress.